Static random access memory (SRAM) is a type of semiconductor memory commonly used to implement fast, low-power storage devices, including registers and primary caches of microprocessors, memories of mobile devices (e.g., mobile phones), etc. An SRAM device generally includes one or more SRAM cells (e.g., an array of SRAM cells), each of which stores the value of a bit. The value of an SRAM cell's bit is written to the cell during a write operation and is read from the cell during a read operation. When idle, an SRAM cell generally consume very little power.
FIG. 1 illustrates a schematic of a five-transistor (“5T”) SRAM cell 100. The 5T SRAM cell 100 includes a bistable latch 110, which is formed using two CMOS inverters (120, 130). These inverters are cross-coupled, such that the output 126 of the first inverter 120 is coupled to the input 138 of the second inverter 130, and the output 136 of the second inverter 130 is coupled to the input 128 of the first inverter 120. The 5T SRAM cell 100 stores the value of its bit at the output 126 of the first inverter, and stores the inverse bit value at the output 136 of the second inverter.
The first CMOS inverter 120 includes a p-channel metal oxide semiconductor (MOS) field effect transistor (FET) (pFET) 122 and an n-channel MOSFET (nFET) 124. The gates of the pFET 122 and nFET 124 are coupled together at the input 128 of the first inverter 120, and the drains of the pFET 122 and nFET 124 are coupled together at the output 126 of the first inverter 120. Likewise, the second CMOS inverter 130 includes a pFET 132 and an nFET 134, with the gates of the pFET 132 and nFET 134 coupled together at the input 138 of the second inverter 130, and with the drains of the pFET 132 and nFET 134 coupled together at the output 136 of the second inverter 130. The sources of the pFETs (122, 132) are coupled to a first power supply rail 112 (which may provide a power supply voltage Vdd), and the sources of the nFETs (124, 134) are coupled to a second power supply rail 114 (which may provide a ground voltage Vss).
In addition, the 5T SRAM cell 100 includes an access FET 140, which controls access to the value of the SRAM cell's bit during read and write operations. The gate of the access FET 140 is coupled to a word line 160. One diffusion terminal of the access FET 140 is coupled to the node 126 that stores the value of the SRAM cell's bit, and the other diffusion terminal of the access FET 140 is coupled to a bit line 150.
In the example of FIG. 1, during a read operation, the access transistor 140 is activated (e.g., by driving a logic-1 value onto the word line 160), thereby coupling the bit line 150 to the output 126 of the inverter 120. The inverter 120 then drives the bit value of the cell 100 onto the bit line 150. During a write operation, the access transistor 140 is activated and the bit value to be written into the cell 100 is driven onto the bit line 150 by a memory controller.
If the bit value being written into the cell 100 differs from the bit value already stored in the cell, a write operation can lead to contention between a pull-up device and a pull-down device. For example, if the cell 100 already stores a logic-0 value at node 126, and a memory controller attempts to write a logic-1 value into the cell 100, a pull-up device in the memory controller attempts to pull up the potential of the node 126 toward Vdd, while the nFET 124 attempts to maintain the node's logic-0 value by pulling down the potential of the node 126 toward Vss. In a well-designed memory system, the sizes and drive strengths of the devices in the SRAM cells, array, and controller are generally set such that the devices used to write bit values into the SRAM cells can reliably overpower the devices within the SRAM cell, such that bit values can be reliably written into the SRAM cells.
Reducing the power consumption of SRAMs and many other computing devices generally reduces the cost of operating such devices and tends to extend the battery life of mobile devices. One common approach to reducing a device's power consumption is to reduce the power supply voltage provided to the device, thereby lowering the device's dynamic power consumption and leakage current. In some cases, the supply voltage to a device may be reduced to the threshold region (e.g., reduced to a value roughly equal to the threshold voltage of the device's transistors) or even to the sub-threshold region (e.g., reduced to a value below the threshold voltage of the device's transistors).
In addition to reducing power consumption, lowering a device's power supply voltage can also reduce the device's reliability by making the device's performance more susceptible to process variation. During the fabrication of an integrated circuit (“IC” or “chip”), naturally occurring variations in the fabrication process can lead to variations in the parameters of the chip's transistors, including channel width, channel length, drive strength, oxide thickness, etc. The sensitivity of transistor parameters to process variation tends to increase as the size of the process node decreases, because the variation in a parameter's value becomes a larger percentage of the parameter's nominal value as the dimensions of the transistor's parameters decrease. In addition, the sensitivity of circuit parameters to process variation tends to increase as the circuit's supply voltage decreases. The impact of process variation on the overall performance of a device can be particularly significant at process nodes smaller than 65 nm and/or when the device's transistors are operated in the sub-threshold region. In some cases, process variation can cause conventional SRAM systems and operations to fail.